Chrono-Scheduling; a simplified dynamic scheduling algorithm for timing predictable processors

We propose a simpler and latency-reduced instruction scheduler, called chronoscheduling algorithm, which avoids large and difficult instruction wake-up in order to reduce power consumption and latencies. The key idea of this scheduler is to extract and record all possible information about the futur...

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Detalhes bibliográficos
Autores: Díaz del Río, Fernando, Sevillano Ramos, José Luis, Vicente Díaz, Saturnino, Jiménez Moreno, Gabriel, Civit Balcells, Antón
Tipo de documento: artigo
Estado:Versão publicada
Data de publicação:2009
País:España
Recursos:Universidad de Sevilla (US)
Repositório:idUS. Depósito de Investigación de la Universidad de Sevilla
OAI Identifier:oai:idus.us.es:11441/143130
Acesso em linha:https://hdl.handle.net/11441/143130
https://doi.org/10.1142/S0218126609005137
Access Level:Acceso aberto
Palavra-chave:Computer architecture
instruction level parallelism
dynamic scheduling
reservation stations
reservation tables
time-predictable processors
Descrição
Resumo:We propose a simpler and latency-reduced instruction scheduler, called chronoscheduling algorithm, which avoids large and difficult instruction wake-up in order to reduce power consumption and latencies. The key idea of this scheduler is to extract and record all possible information about the future execution of an instruction during its issue, so as not to look for this information again and again during wait stages at the reservation stations. Therefore, an instruction can be issued with the information about at what cycle its operands must be captured and when it must be executed. The first implementation is targeted to processors that have constant latencies like many embedded microcontrollers, most vector processors without data cache, etc. Its main advantages are: no tags, no renaming, and much simpler waiting stations. When compared with classical dynamic schedulers, chrono-scheduling provides approximately the same CPI but with simpler overall circuitry and presumably higher clock speed (mainly because of its simplified stations).