COMPAD: A heterogeneous cache-scratchpad CPU architecture with data layout compaction for embedded loop-dominated applications

The growing trend of pervasive computing has consolidated the everlasting need for power efficient devices. The conventional cache subsystem of general-purpose CPUs, while being able to adapt to many use cases, suffers from energy inefficiencies in some scenarios. It is well-known by now in the acad...

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Detalles Bibliográficos
Autores: Marinelli, Tommaso, Gómez Pérez, José Ignacio, Tenllado Van Der Reijden, Christian Tomás, Catthoor, Francky
Tipo de recurso: artículo
Fecha de publicación:2023
País:España
Institución:Universidad Complutense de Madrid (UCM)
Repositorio:Docta Complutense
Idioma:inglés
OAI Identifier:oai:docta.ucm.es:20.500.14352/88544
Acceso en línea:https://hdl.handle.net/20.500.14352/88544
Access Level:acceso abierto
Palabra clave:Cache
Compaction
Energy efficiency
Data reuse
Scratchpad
Informática (Informática)
1203.17 Informática
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repository_id_str
spelling COMPAD: A heterogeneous cache-scratchpad CPU architecture with data layout compaction for embedded loop-dominated applicationsMarinelli, TommasoGómez Pérez, José IgnacioTenllado Van Der Reijden, Christian TomásCatthoor, FranckyCacheCompactionEnergy efficiencyData reuseScratchpadInformática (Informática)1203.17 InformáticaThe growing trend of pervasive computing has consolidated the everlasting need for power efficient devices. The conventional cache subsystem of general-purpose CPUs, while being able to adapt to many use cases, suffers from energy inefficiencies in some scenarios. It is well-known by now in the academic literature that the utilization of a scratchpad memory (SPM) can help reducing the overall energy consumption of embedded systems. This work proposes a hybrid cache-SPM architecture with support logic for semi-transparent data management and spatial locality improvement. Selected data are transferred and stored in the SPM in a compact form using dynamic layout transformation. As a second major contribution, we introduce a methodology to identify memory access sequences that make an inefficient use of the cache, marking them as candidates to be moved to an SPM of constrained space. The methodology does not require access to the source code of the target applications, relying on binary instrumentation and offline profiling. The resulting mapping policies have been tested on a simulated system, showing a mean memory dynamic energy reduction of 43% and a mean speed gain of 13% with a representative benchmark set.ElsevierUniversidad Complutense de Madrid20232023-10-2920232023-10-29journal articlehttp://purl.org/coar/resource_type/c_6501info:eu-repo/semantics/articleapplication/pdfhttps://hdl.handle.net/20.500.14352/88544reponame:Docta Complutenseinstname:Universidad Complutense de Madrid (UCM)Inglésengopen accesshttp://purl.org/coar/access_right/c_abf2Attribution-NonCommercial 4.0 Internationalhttp://creativecommons.org/licenses/by-nc/4.0/info:eu-repo/semantics/openAccessoai:docta.ucm.es:20.500.14352/885442026-06-02T12:44:21Z
dc.title.none.fl_str_mv COMPAD: A heterogeneous cache-scratchpad CPU architecture with data layout compaction for embedded loop-dominated applications
title COMPAD: A heterogeneous cache-scratchpad CPU architecture with data layout compaction for embedded loop-dominated applications
spellingShingle COMPAD: A heterogeneous cache-scratchpad CPU architecture with data layout compaction for embedded loop-dominated applications
Marinelli, Tommaso
Cache
Compaction
Energy efficiency
Data reuse
Scratchpad
Informática (Informática)
1203.17 Informática
title_short COMPAD: A heterogeneous cache-scratchpad CPU architecture with data layout compaction for embedded loop-dominated applications
title_full COMPAD: A heterogeneous cache-scratchpad CPU architecture with data layout compaction for embedded loop-dominated applications
title_fullStr COMPAD: A heterogeneous cache-scratchpad CPU architecture with data layout compaction for embedded loop-dominated applications
title_full_unstemmed COMPAD: A heterogeneous cache-scratchpad CPU architecture with data layout compaction for embedded loop-dominated applications
title_sort COMPAD: A heterogeneous cache-scratchpad CPU architecture with data layout compaction for embedded loop-dominated applications
dc.creator.none.fl_str_mv Marinelli, Tommaso
Gómez Pérez, José Ignacio
Tenllado Van Der Reijden, Christian Tomás
Catthoor, Francky
author Marinelli, Tommaso
author_facet Marinelli, Tommaso
Gómez Pérez, José Ignacio
Tenllado Van Der Reijden, Christian Tomás
Catthoor, Francky
author_role author
author2 Gómez Pérez, José Ignacio
Tenllado Van Der Reijden, Christian Tomás
Catthoor, Francky
author2_role author
author
author
dc.contributor.none.fl_str_mv Universidad Complutense de Madrid
dc.subject.none.fl_str_mv Cache
Compaction
Energy efficiency
Data reuse
Scratchpad
Informática (Informática)
1203.17 Informática
topic Cache
Compaction
Energy efficiency
Data reuse
Scratchpad
Informática (Informática)
1203.17 Informática
description The growing trend of pervasive computing has consolidated the everlasting need for power efficient devices. The conventional cache subsystem of general-purpose CPUs, while being able to adapt to many use cases, suffers from energy inefficiencies in some scenarios. It is well-known by now in the academic literature that the utilization of a scratchpad memory (SPM) can help reducing the overall energy consumption of embedded systems. This work proposes a hybrid cache-SPM architecture with support logic for semi-transparent data management and spatial locality improvement. Selected data are transferred and stored in the SPM in a compact form using dynamic layout transformation. As a second major contribution, we introduce a methodology to identify memory access sequences that make an inefficient use of the cache, marking them as candidates to be moved to an SPM of constrained space. The methodology does not require access to the source code of the target applications, relying on binary instrumentation and offline profiling. The resulting mapping policies have been tested on a simulated system, showing a mean memory dynamic energy reduction of 43% and a mean speed gain of 13% with a representative benchmark set.
publishDate 2023
dc.date.none.fl_str_mv 2023
2023-10-29
2023
2023-10-29
dc.type.none.fl_str_mv journal article
http://purl.org/coar/resource_type/c_6501
dc.type.openaire.fl_str_mv info:eu-repo/semantics/article
format article
dc.identifier.none.fl_str_mv https://hdl.handle.net/20.500.14352/88544
url https://hdl.handle.net/20.500.14352/88544
dc.language.none.fl_str_mv Inglés
eng
language_invalid_str_mv Inglés
language eng
dc.rights.none.fl_str_mv open access
http://purl.org/coar/access_right/c_abf2
Attribution-NonCommercial 4.0 International
http://creativecommons.org/licenses/by-nc/4.0/
dc.rights.openaire.fl_str_mv info:eu-repo/semantics/openAccess
rights_invalid_str_mv open access
http://purl.org/coar/access_right/c_abf2
Attribution-NonCommercial 4.0 International
http://creativecommons.org/licenses/by-nc/4.0/
eu_rights_str_mv openAccess
dc.format.none.fl_str_mv application/pdf
dc.publisher.none.fl_str_mv Elsevier
publisher.none.fl_str_mv Elsevier
dc.source.none.fl_str_mv reponame:Docta Complutense
instname:Universidad Complutense de Madrid (UCM)
instname_str Universidad Complutense de Madrid (UCM)
reponame_str Docta Complutense
collection Docta Complutense
repository.name.fl_str_mv
repository.mail.fl_str_mv
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score 15,300719

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