Design Space Exploration of Next-Generation HPC Machines

The landscape of High Performance Computing (HPC) system architectures keeps expanding with new technologies and increased complexity. With the goal of improving the efficiency of next-generation large HPC systems, designers require tools for analyzing and predicting the impact of new architectural...

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Detalhes bibliográficos
Autores: Gómez, Constantino, Martínez, Francesc, Armejach Sanosa, Adrià|||0000-0003-2869-668X, Moretó Planas, Miquel|||0000-0002-9848-8758, Mantovani, Filippo|||0000-0003-3559-4825, Casas, Marc|||0000-0003-4564-2093
Tipo de documento: relatório científico
Data de publicação:2019
País:España
Recursos:Universitat Politècnica de Catalunya (UPC)
Repositório:UPCommons. Portal del coneixement obert de la UPC
Idioma:inglês
OAI Identifier:oai:upcommons.upc.edu:2117/131511
Acesso em linha:https://hdl.handle.net/2117/131511
Access Level:Acceso aberto
Palavra-chave:High performance computing
HPC
Co-design
Parallelism
OpenMP
MPI
Next-generation architectures
Supercomputadors
Àrees temàtiques de la UPC::Informàtica
Descrição
Resumo:The landscape of High Performance Computing (HPC) system architectures keeps expanding with new technologies and increased complexity. With the goal of improving the efficiency of next-generation large HPC systems, designers require tools for analyzing and predicting the impact of new architectural features on the performance of complex scientific applications at scale. We simulate five hybrid (MPI+OpenMP) applications over 864 architectural proposals based on stateof-the-art and emerging HPC technologies, relevant both in industry and research. This paper significantly extends our previous work with MUltiscale Simulation Approach (MUSA) enabling accurate performance and power estimations of largescale HPC systems. We reveal that several applications present critical scalability issues mostly due to the software parallelization approach. Looking at speedup and energy consumption exploring the design space (i.e., changing memory bandwidth, number of cores, and type of cores), we provide evidence-based architectural recommendations that will serve as hardware and software codesign guidelines.