Design of MOS-translinear multiplier/dividers in analog VLSI
A general framework for designing current-mode CMOS analog multiplier/divider circuits based on the cascade connection of a geometric-mean circuit and a squarer/ divider is presented. It is shown how both building blocks can be readily obtained from a generic second-order MOS translinear loop. Vario...
| Autores: | , |
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| Tipo de recurso: | artículo |
| Estado: | Versión publicada |
| Fecha de publicación: | 2000 |
| País: | España |
| Institución: | Universidad Pública de Navarra |
| Repositorio: | Academica-e. Repositorio Institucional de la Universidad Pública de Navarra |
| OAI Identifier: | oai:academica-e.unavarra.es:2454/23543 |
| Acceso en línea: | https://hdl.handle.net/2454/23543 |
| Access Level: | acceso abierto |
| Palabra clave: | Analog multiplier/dividers Multipliers MOS-translinear Voltage-translinear CMOS analog circuits Analog VLSI |
| Sumario: | A general framework for designing current-mode CMOS analog multiplier/divider circuits based on the cascade connection of a geometric-mean circuit and a squarer/ divider is presented. It is shown how both building blocks can be readily obtained from a generic second-order MOS translinear loop. Various implementations are proposed, featuring simplicity, favorable precision and wide dynamic range. They can be successfully employed in a wide range of analog VLSI processing tasks. Experimental results of two versions, based on stacked and folded MOS-translinear loops and fabricated in a 2.4-1am CMOS process, are provided in order to verify the correctness of the proposed approach. |
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