A comparative analysis of cache memory architectures for the multiplus multiprocessor
This paper analyses some design altematives for the MULTIPLUS cache memory subsystem architecture. MUL TIPLUS is a high performance multiprocessor system under development at NCE/UFRJ. The analysis is carried out using a simu1ator which supports different cache configurations. The simulator experime...
| Authors: | , , |
|---|---|
| Format: | report |
| Status: | Published version |
| Publication Date: | 1992 |
| Country: | Brasil |
| Institution: | Universidade Federal do Rio de Janeiro (UFRJ) |
| Repository: | Repositório Institucional da UFRJ |
| Language: | English |
| OAI Identifier: | oai:pantheon.ufrj.br:11422/1073 |
| Online Access: | http://hdl.handle.net/11422/1073 |
| Access Level: | Open access |
| Keyword: | Arquitetura de memória cache Multiprocessador MULTIPLUS Cache memory architecture CNPQ::CIENCIAS EXATAS E DA TERRA::CIENCIA DA COMPUTACAO |
| Summary: | This paper analyses some design altematives for the MULTIPLUS cache memory subsystem architecture. MUL TIPLUS is a high performance multiprocessor system under development at NCE/UFRJ. The analysis is carried out using a simu1ator which supports different cache configurations. The simulator experiments have been done under three different situations: a non-cache system and the use of write back and write through control policies. The graphical results show the system behaviour in relation to the average ratio of bus occupation and the average processor cycle length. |
|---|