Um núcleo inteligente para processamento distribuído de resolvedores SAT em verificação por equivalências
Equivalence Checking is one the of the key components in formal verification for digital systems. It is also one of the most widely used approaches in industry for functional equivalence verification of different designs. A number of recently proposed BDD and SAT based approaches have met with consi...
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| Tipo de recurso: | tesis de maestría |
| Estado: | Versión publicada |
| Fecha de publicación: | 2006 |
| País: | Brasil |
| Institución: | Universidade Federal de Minas Gerais (UFMG) |
| Repositorio: | Repositório Institucional da UFMG |
| Idioma: | portugués |
| OAI Identifier: | oai:repositorio.ufmg.br:1843/RVMR-6TJRJ6 |
| Acceso en línea: | http://hdl.handle.net/1843/RVMR-6TJRJ6 |
| Access Level: | acceso abierto |
| Palabra clave: | processamento distribuido Circuitos eletronicos Projetos Processamento de dados Computação Circuitos integrados Verificação Processamento eletrônico de dados Processamento distribuído |
| Sumario: | Equivalence Checking is one the of the key components in formal verification for digital systems. It is also one of the most widely used approaches in industry for functional equivalence verification of different designs. A number of recently proposed BDD and SAT based approaches have met with considerable success in this area. However, the growing gap between the current solvers capabilities and the increasing complexity in digital designs lead to exploring alternative, better solutions. This work proposes an intelligent kernel for distributed processing of SAT solvers in Equivalence Checking. Specifically, the proposed kernel exploits a new technique for identifying structural similarities between the circuits. Finally, results of verification using the proposed methodology are presented. |
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