Maze routing steiner trees with delay versus wire length tradeoff
In this paper, we address the problem of generating good topologies of rectilinear Steiner trees using path search algorithms. Various techniques have been applied in order to achieve acceptable run times on a Maze Router that builds Steiner trees. A biasing technique proposed for wire length improv...
| Autores: | , , , |
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| Formato: | artículo |
| Estado: | Versión publicada |
| Fecha de publicación: | 2009 |
| País: | Brasil |
| Recursos: | Universidade Federal do Rio Grande do Sul (UFRGS) |
| Repositorio: | Repositório Institucional da UFRGS |
| Idioma: | inglés |
| OAI Identifier: | oai:www.lume.ufrgs.br:10183/27623 |
| Acesso em linha: | http://hdl.handle.net/10183/27623 |
| Access Level: | acceso abierto |
| Palavra-chave: | Microeletrônica Vlsi Delay Maze search Routing Steiner trees |
| Resumo: | In this paper, we address the problem of generating good topologies of rectilinear Steiner trees using path search algorithms. Various techniques have been applied in order to achieve acceptable run times on a Maze Router that builds Steiner trees. A biasing technique proposed for wire length improvement, produces trees that are within 2% from optimal topologies in average. By introducing a sharing factor and a path-length factor we show how to trade-off wire length for delay. Experimental results show that our algorithm generates topologies with better delay compared to state of the art heuristics for Steiner trees, such as AHHK (from 26% to 40%) and P-Trees (from 1% to 30% and from 6% to 21% in the presence of blockages) while keeping the properties of a routing algorithm. An important motivation for this work lies in the fact that it can be used for estimation in the early stages as well as for actual routing, thereby improving the convergence and timing closure of the design significantly.We also provide some valuable theoretical background and insights on delay optimization and on how it relates to our maze router implementation. |
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