VHDL-based programming environment for Floating-Gate analog memory cell
An implementation in CMOS technology of a Floating-Gate Analog Memory Cell and Programming Environment is presented. A digital closed-loop control compares a reference value set by user and the memory output and after cycling, the memory output is updated and the new value stored. The circuit can be...
| Autores: | , |
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| Tipo de recurso: | artículo |
| Estado: | Versión publicada |
| Fecha de publicación: | 2005 |
| País: | Brasil |
| Institución: | Universidade Estadual de Londrina (UEL) |
| Repositorio: | Revista Semina: Ciências Exatas e Tecnológicas (Online) |
| Idioma: | portugués |
| OAI Identifier: | oai:ojs2.ojs.uel.br:article/1581 |
| Acceso en línea: | https://ojs.uel.br/revistas/uel/index.php/semexatas/article/view/1581 |
| Access Level: | acceso abierto |
| Palabra clave: | Floating-Gate Trimming VHDL. Dispositivos |
| Sumario: | An implementation in CMOS technology of a Floating-Gate Analog Memory Cell and Programming Environment is presented. A digital closed-loop control compares a reference value set by user and the memory output and after cycling, the memory output is updated and the new value stored. The circuit can be used as analog trimming for VLSI applications where mechanical trimming associated with postprocessing chip is prohibitive due to high costs. |
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