A cryptography core tolerant to DFA fault attacks
This work describes a hardware approach for the concurrent fault detection and error correction in a cryptographic core. It has been shown in the literature that transient faults injected in a cryptographic core can lead to the revelation of the encryption key using quite inexpensive equipments. Thi...
| Autores: | , , |
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| Tipo de recurso: | artículo |
| Estado: | Versión publicada |
| Fecha de publicación: | 2007 |
| País: | Brasil |
| Institución: | Universidade Federal do Rio Grande do Sul (UFRGS) |
| Repositorio: | Repositório Institucional da UFRGS |
| Idioma: | inglés |
| OAI Identifier: | oai:www.lume.ufrgs.br:10183/271340 |
| Acceso en línea: | http://hdl.handle.net/10183/271340 |
| Access Level: | acceso abierto |
| Palabra clave: | Microeletrônica Smart ards Cryptography Fault attacks Fault tolerance |
| Sumario: | This work describes a hardware approach for the concurrent fault detection and error correction in a cryptographic core. It has been shown in the literature that transient faults injected in a cryptographic core can lead to the revelation of the encryption key using quite inexpensive equipments. This kind of attack is a real threat to tamper resistant devices like Smart Cards. To tackle such attacks, the cryptographic core must be immune to transient faults. In this work the DES algorithm is taken as a vulnerable cryptosystem case study. We show how an attack against DES is performed through a fault injection campaign. Then, a countermeasure based on partial hardware replication is proposed and applied to DES. Experimental results show the efficiency of the proposed scheme to protect DES against DFA fault attacks. Furthermore, the proposed solution is independent of implementation, and can be applied to other cryptographic algorithms, such as AES. |
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