Real-time low-distortion digital PWM modulator for switching converters

A compensation scheme to reduce the inherent baseband distortion in uniform PWM modulators (UPWM) is presented in this paper. The method is based on real-time mapping of the switching times of UPWM to those of natural PWM that, as it is well-known, exhibits far less in-band distortion. Two alternati...

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Detalles Bibliográficos
Autores: Chierchie, Fernando, Soto, Angel Jose, Paolini, Eduardo Emilio, Oliva, Alejandro Raul
Tipo de recurso: artículo
Estado:Versión publicada
Fecha de publicación:2012
País:Argentina
Institución:Consejo Nacional de Investigaciones Científicas y Técnicas
Repositorio:CONICET Digital (CONICET)
Idioma:inglés
OAI Identifier:oai:ri.conicet.gov.ar:11336/139375
Acceso en línea:http://hdl.handle.net/11336/139375
Access Level:acceso abierto
Palabra clave:FIELD PROGRAMMABLE GATE ARRAYS
HARMONIC DISTORTION
PULSE WIDTH MODULATION
SWITCHING CONVERTERS
https://purl.org/becyt/ford/2.2
https://purl.org/becyt/ford/2
Descripción
Sumario:A compensation scheme to reduce the inherent baseband distortion in uniform PWM modulators (UPWM) is presented in this paper. The method is based on real-time mapping of the switching times of UPWM to those of natural PWM that, as it is well-known, exhibits far less in-band distortion. Two alternatives are presented: one based on an exact, analytic algorithm recently reported in the literature, and another one that uses an artificial neural network (ANN). Both methods are designed for arbitrary, band-limited modulating signals and they are not restricted to single-frequency sinusoids, as other techniques presented in the literature. Simulation results and experimental measurements of a FPGA implementation demonstrate a significant reduction of the distortion in real-time applications. The performance of both alternatives is compared for several modulating signals, and the results of industry-standard distortion tests are also reported. Finally, some guidelines for choosing the best alternative for ASIC or FPGA implementations are provided