Castells Rufas, D., Marco Sola, S., Moure, J. C., Aguado, Q., & Espinosa, A. (2022). FPGA Acceleration of Pre-Alignment Filters for Short Read Mapping With HLS.

Castells Rufas, David, Santiago|||0000-0001-7951-3914 Marco Sola, Juan Carlos Moure, Quim Aguado, and Antonio Espinosa. FPGA Acceleration of Pre-Alignment Filters for Short Read Mapping With HLS. 2022.

Castells Rufas, David, et al. FPGA Acceleration of Pre-Alignment Filters for Short Read Mapping With HLS. 2022.