A flexible system-on-chip FPGA architecture for prototyping experimental GNSS receivers
(English) The rapid evolution in satellite navigation technology (GNSS) requires advanced prototyping tools for exploring new signals and developing innovative systems. Prototyping is essential in the design and development process, as it allows researchers to test and refine their ideas before impl...
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| Tipo de recurso: | tesis doctoral |
| Estado: | Versión publicada |
| Fecha de publicación: | 2024 |
| País: | España |
| Institución: | CBUC, CESCA |
| Repositorio: | TDR. Tesis Doctorales en Red |
| OAI Identifier: | oai:www.tdx.cat:10803/691253 |
| Acceso en línea: | http://hdl.handle.net/10803/691253 https://dx.doi.org/10.5821/dissertation-2117-409131 |
| Access Level: | acceso abierto |
| Palabra clave: | Àrees temàtiques de la UPC::Enginyeria de la telecomunicació 621.3 |
| Sumario: | (English) The rapid evolution in satellite navigation technology (GNSS) requires advanced prototyping tools for exploring new signals and developing innovative systems. Prototyping is essential in the design and development process, as it allows researchers to test and refine their ideas before implementing them on a large scale. Prototyping using commercial GNSS receivers poses several challenges. Currently, these receivers are primarily based on application-specific integrated circuits (ASICs), which are characterized by low power consumption, compact dimensions, and low cost, but offer limited flexibility. Although some commercial devices incorporate software-defined radio (SDR) techniques, they often contain proprietary code that restricts reconfiguration through an application programming interface (API) established by the manufacturer. GNSS receivers based on free and open-source software have become very valuable resources in the field of research and development, especially in satellite navigation. These receivers are highly valued for their adaptability and flexibility, allowing researchers to tailor the software to specific experimental needs or develop new signal processing algorithms. However, software-defined receivers tend to be less energy-efficient compared to hardware-based receivers, as they operate on general-purpose processors, which are not optimized for low power consumption. This thesis focuses on the design and development of a low-cost architecture for prototyping experimental GNSS receivers, based on System-on-Chip Field Programmable Gate Arrays (SoC FPGAs). This architecture overcomes the limitations of commercial GNSS receivers in terms of adaptability, flexibility, and reprogramming capacity, and offers improved energy efficiency compared to software-based receivers that rely on general-purpose processors. The strategy consists of combining the versatility of software-defined radio with the intensive parallelism and optimized energy consumption of programmable logic devices, providing the best of both worlds. This fusion allows the development of compact, portable GNSS receivers, thus facilitating the prototyping of embedded devices suitable for field testing. In addition, the GNSS processing core is based on a free and open-source software implementation, which provides detailed access to the signal processing chain and allows unrestricted exploration and modification of the algorithms used. This thesis also presents a design methodology for the development of new prototypes and new GNSS signal processing algorithms based on the proposed SoC FPGA architecture. This methodology places special emphasis on code reuse, a key aspect for reducing development costs and time. The practical applications of this architecture have been demonstrated through three prototypes: a GNSS receiver for low Earth orbit (LEO), a GNSS signal repeater, and a high-sensitivity GNSS receiver. The innovative approach presented in this thesis facilitates the development of experimental prototypes of flexible and portable GNSS receivers and signal generators, suitable for both laboratory experiments and field testing. |
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